Ultrascale+ PL Full/Partial configuration

Page Contents

Using Processor Configuration Access Port (PCAP)
Using Internal Configuration Access Port (ICAP)
- Dynamic Function eXchange (DFX)

Using Processor Configuration Access Port (PCAP)

Device tree overlays are not supported by Xilinx DTG and must be hand-crafted
Kernel configuration is required
Note, partial reconfiguration of the PL regions requires partioning of the bitstream into blocks so that they can be replaced as part of a higher level bitstream design. As far as I am aware this goal can only be achieved in Xilinx Vivado. There is an indepth tutorial here

FPGAUTIL

Command line tool that can be used in Linux userland to achieve partial or full reconfiguration, DT overlays, etc…

Class Device

This uses the Linux device filesystem to achieve partial or full reconfiguration.This is done by writing to the fpga_manager device.

See this wiki for more detail

Xilinx Baremetal Drivers

This uses a hardware abstraction layer provided by Xilinx. Source code can be found in xilfpga.

The toplevel function call is XFpga_BitStream_Load.

This uses the low level XilinxProcessorIPLib drivers to update the PL region viaInter Processor Interrupts (IPI)[1]. The key IPI low level functions can be found in ipipsu.c

Note, thePlatform Management Unit Firmware (PMUFW)also uses this low level driver to access the PL during the boot phase. See the Handling-Inter-Process-Interrupts-in-PMU-firmware section in the Software Developer Guide for further details.

[1] IPI Interrupts and Message Buffers

Using Internal Configuration Access Port (ICAP)

Dynamic Function eXchange (DFX)

This uses PL IP blocks (DFX) to partially reconfigure PL regions during runtime. It is more performant than software methods but ICAP cannot be enabled at the same time as PCAP:

Dynamic-Function-eXchange-through-ICAP-for-Zynq-Devices

Vivado 2022.1 – Dynamic Function eXchange homepage

A Linux userland library is avaiable to use with DFX